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| PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT PD161831 240/244-OUTPUT TFT-LCD SOURCE DRIVER WITH TIMING GENERATOR (COMPATIBLE WITH 64-GRAY SCALES) DESCRIPTION The PD161831 is a source driver for LIPS TFTs with on-chip timing generator and featuring 240/244 outputs. Data input as 6-bit x 3-dot digital data is output as 64 -corrected values using an internal D/A converter, achieving 260,000-color (full-color) display. FEATURES * CMOS level input * 240/244 outputs (R, G, B output) * Input of 6 bits (gray-scale data) by 3 dots * Capable of outputting 64 values by means of 5 external power modules and a D/A converter * Output dynamic range: VSS + 0.05 V to VS - 0.05 V * High-speed data transfer: fCLK = 20 MHz MAX. (during 2-times data transfer when operating at VCC = 2.5 V. During 1-time data transfer 10 MHz MAX.) * High-speed data transfer: fCLK = 16 MHz MAX. (during 2-times data transfer when operating at VCC = 2.2 V. During 1-time data transfer 8 MHz MAX.) * On-chip power supplies (driver power supply, gate top power supply, gate bottom power supply) * Logic power supply voltage (VCC): 2.2 to 3.6 V * DC/DC reference power supply (VDC): 2.5 to 3.6 V * On-chip timing generator (Outputs R, G, B switching signal to panel. Outputs gate control signal.) * On-chip 8-bit serial interface (applied to SPI) ORDERING INFORMATION Part Number Package Chip PD161831P Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives. The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S16269EJ2V0PM00 (2nd edition) Date Published October 2002 NS CP (K) Printed in Japan The mark 5 shows major revised points. (c) 2002 PD161831 5 1. BLOCK DIAGRAM C1+/- DC/DC converter C2+/- VDC2 VDC C3+/- C4+/- C5+/- VGD VDD2 DC/DC converter VSS1 VSS2 DCCLK VCC VSS1 VDC SCLK SI SO LCDCS SCLEG0 SCLEG1 /CS1 CS2 SCLK_SUB SO_SUB A0 D00-D05 D10-D15 D20-D25 DCK CKS OSC MAS,/SLV /RESET VSYNC HSYNC VREF TESTOUT TESTIN1 TESTIN2 TESTIN3 TESTIN4 VR VS Serial Interface Command Decoder Timing Controler VCOM Buffer COMDCIN COMDCSL COMDC COMC VCOMH 244-bit bidirectional shift register RGB Interface VDD2 RSW_O GSW_O BSW_O EXT1_O EXT2_O EXT3_O STHR STHL Data register TCON L/S VSS2/3 RSW_I GSW_I BSW_I EXT1_I EXT2_I EXT3_I VDD2 Multiplex Switch Control Data latch Data Latch Control POL AP STB RGB SW HSEG VSEG TEST_COM2 TEST_VCLAMP GCLK_O GSTB_O GOE1_O GOE2_O GR,/L_O L/S VSS2/3 GCLK_I GSTB_I GOE1_I GOE2_I GAM V0-V4 PVCC Gate Control Level shifter PVSS BGR_O Control BIAS Control S1 D/A converter Output buffer S244 Remark /xxx indicates active low signal. 2 Preliminary Product Information S16269EJ2V0PM PD161831 2. PIN CONFIGURATION (Pad Layout) Chip size: T.B.D. Bump size: INPUT/VCOM/TEST/DUMMY: 50 x 75 m OUTPUT: 35 x 100 m 2 2 Remark T.B.D.: To be determined. Alignment Mark (Unit: m) X Coordinate Alignment1 Alignment2 Aluminum (core) Bump (core) Aluminum (core) Bump (core) 10768.0 10768.0 -10768.0 -10768.0 Y Coordinate 441.0 366.0 441.0 366.0 Remark The figures are rounded off in 0.5 m units. Alignment2 Alignment1 Driver output side Input/output side Alminum 50 m 50 m Bump 50 m 50 m Preliminary Product Information S16269EJ2V0PM 3 PD161831 Table 2-1. Pad Layout (1/2) No. PAD Name 1 Dummy 2 Dummy 3 Dummy 4 Dummy 5 S244 6 S243 7 S242 8 S241 9 S240 10 S239 11 S238 12 S237 13 S236 14 S235 15 S234 16 S233 17 S232 18 S231 19 S230 20 S229 21 S228 22 S227 23 S226 24 S225 25 S224 26 S223 27 S222 28 S221 29 S220 30 S219 31 S218 32 S217 33 S216 34 S215 35 S214 36 S213 37 S212 38 S211 39 S210 40 S209 41 S208 42 S207 43 S206 44 S205 45 S204 46 S203 47 S202 48 S201 49 S200 50 S199 51 S198 52 S197 53 S196 54 S195 55 S194 56 S193 57 S192 58 S191 59 S190 60 S189 61 S188 62 S187 63 S186 64 S185 65 S184 66 S183 67 S182 68 S181 69 S180 70 S179 X [m] 10797.00 10737.00 10677.00 9840.00 9780.00 9720.00 9660.00 9600.00 9540.00 9480.00 9420.00 9360.00 9300.00 9240.00 9180.00 9120.00 9060.00 9000.00 8940.00 8880.00 8820.00 8760.00 8700.00 8640.00 8580.00 8520.00 8460.00 8400.00 8340.00 8280.00 8220.00 8160.00 8100.00 8040.00 7980.00 7920.00 7860.00 7800.00 7740.00 7680.00 7620.00 7560.00 7500.00 7440.00 7380.00 7320.00 7260.00 7200.00 7140.00 7080.00 7020.00 6960.00 6900.00 6840.00 6780.00 6720.00 6660.00 6600.00 6540.00 6480.00 6420.00 6360.00 6300.00 6240.00 6180.00 6120.00 6060.00 6000.00 5940.00 5880.00 Y [m] 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 No. PAD Name 71 S178 72 S177 73 S176 74 S175 75 S174 76 S173 77 S172 78 S171 79 S170 80 S169 81 S168 82 S167 83 S166 84 S165 85 S164 86 S163 87 S162 88 S161 89 S160 90 S159 91 S158 92 S157 93 S156 94 S155 95 S154 96 S153 97 S152 98 S151 99 S150 100 S149 101 S148 102 S147 103 S146 104 S145 105 S144 106 S143 107 S142 108 S141 109 S140 110 S139 111 S138 112 S137 113 S136 114 S135 115 S134 116 S133 117 S132 118 S131 119 S130 120 S129 121 S128 122 S127 123 S126 124 S125 125 S124 126 S123 127 S122 128 S121 129 S120 130 S119 131 S118 132 S117 133 S116 134 S115 135 S114 136 S113 137 S112 138 S111 139 S110 140 S109 X [m] 5820.00 5760.00 5700.00 5640.00 5580.00 5520.00 5460.00 5400.00 5340.00 5280.00 5220.00 5160.00 5100.00 5040.00 4980.00 4920.00 4860.00 4800.00 4740.00 4680.00 4620.00 4560.00 4500.00 4440.00 4380.00 4320.00 4260.00 4200.00 4140.00 4080.00 4020.00 3960.00 3900.00 3840.00 3780.00 3720.00 3660.00 3600.00 3540.00 3480.00 3420.00 3360.00 3300.00 3240.00 3180.00 3120.00 3060.00 3000.00 2940.00 2880.00 2820.00 2760.00 2700.00 2640.00 2580.00 2520.00 2460.00 2400.00 2340.00 2280.00 2220.00 2160.00 2100.00 2040.00 1980.00 1920.00 1860.00 1800.00 1740.00 1680.00 Y [m] 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 No. PAD Name 141 S108 142 S107 143 S106 144 S105 145 S104 146 S103 147 S102 148 S101 149 S100 150 S99 151 S98 152 S97 153 S96 154 S95 155 S94 156 S93 157 S92 158 S91 159 S90 160 S89 161 S88 162 S87 163 S86 164 S85 165 S84 166 S83 167 S82 168 S81 169 S80 170 S79 171 S78 172 S77 173 S76 174 S75 175 S74 176 S73 177 S72 178 S71 179 S70 180 S69 181 S68 182 S67 183 S66 184 S65 185 S64 186 S63 187 S62 188 S61 189 S60 190 S59 191 S58 192 S57 193 S56 194 S55 195 S54 196 S53 197 S52 198 S51 199 S50 200 S49 201 S48 202 S47 203 S46 204 S45 205 S44 206 S43 207 S42 208 S41 209 S40 210 S39 X [m] 1620.00 1560.00 1500.00 1440.00 1380.00 1320.00 1260.00 1200.00 1140.00 1080.00 1020.00 960.00 900.00 840.00 780.00 720.00 660.00 600.00 540.00 480.00 420.00 360.00 300.00 240.00 180.00 120.00 60.00 0.00 -60.00 -120.00 -180.00 -240.00 -300.00 -360.00 -420.00 -480.00 -540.00 -600.00 -660.00 -720.00 -780.00 -840.00 -900.00 -960.00 -1020.00 -1080.00 -1140.00 -1200.00 -1260.00 -1320.00 -1380.00 -1440.00 -1500.00 -1560.00 -1620.00 -1680.00 -1740.00 -1800.00 -1860.00 -1920.00 -1980.00 -2040.00 -2100.00 -2160.00 -2220.00 -2280.00 -2340.00 -2400.00 -2460.00 -2520.00 Y [m] 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 No. PAD Name 211 S38 212 S37 213 S36 214 S35 215 S34 216 S33 217 S32 218 S31 219 S30 220 S29 221 S28 222 S27 223 S26 224 S25 225 S24 226 S23 227 S22 228 S21 229 S20 230 S19 231 S18 232 S17 233 S16 234 S15 235 S14 236 S13 237 S12 238 S11 239 S10 240 S9 241 S8 242 S7 243 S6 244 S5 245 S4 246 S3 247 S2 248 S1 249 Dummy 250 Dummy 251 Dummy 252 Dummy 253 Dummy 254 Dummy 255 Dummy 256 Dummy 257 Dummy 258 Dummy 259 Dummy 260 Dummy 261 Dummy 262 Dummy 263 Dummy 264 Dummy 265 Dummy 266 Dummy 267 Dummy 268 Dummy 269 Dummy 270 Dummy 271 Dummy 272 Dummy 273 Dummy 274 Dummy 275 Dummy 276 Dummy 277 Dummy 278 Dummy 279 Dummy 280 Dummy X [m] -2580.00 -2640.00 -2700.00 -2760.00 -2820.00 -2880.00 -2940.00 -3000.00 -3060.00 -3120.00 -3180.00 -3240.00 -3300.00 -3360.00 -3420.00 -3480.00 -3540.00 -3600.00 -3660.00 -3720.00 -3780.00 -3840.00 -3900.00 -3960.00 -4020.00 -4080.00 -4140.00 -4200.00 -4260.00 -4320.00 -4380.00 -4440.00 -4500.00 -4560.00 -4620.00 -4680.00 -4740.00 -4800.00 -4860.00 -4920.00 -4980.00 -5040.00 -5100.00 -5160.00 -5220.00 -5280.00 -5340.00 -5400.00 -5460.00 -5520.00 -5580.00 -5640.00 -5700.00 -5760.00 -5820.00 -5880.00 -5940.00 -6000.00 -6060.00 -6120.00 -6180.00 -6240.00 -6300.00 -6360.00 -6420.00 -6480.00 -6540.00 -6600.00 -6660.00 -6720.00 Y [m] 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 4 Preliminary Product Information S16269EJ2V0PM PD161831 Table 2-1. Pad Layout (2/2) No. PAD Name 281 Dummy 282 Dummy 283 BSW_O 284 BSW_O 285 GSW_O 286 GSW_O 287 RSW_O 288 RSW_O 289 EXT3_O 290 EXT3_O 291 EXT2_O 292 EXT2_O 293 EXT1_O 294 EXT1_O 295 VSS2 296 VSS2 297 VSS2 298 VSS2 299 VSS1 300 VSS1 301 VSS1 302 VSS1 303 VDD2 304 VDD2 305 VDD2 306 VDD2 307 GOE2_O 308 GOE2_O 309 GOE2_O 310 GOE2_O 311 GOE1_O 312 GOE1_O 313 GR/L_O 314 GR/L_O 315 GCLK_O 316 GCLK_O 317 GSTB_O 318 GSTB_O 319 Dummy 320 Dummy 321 Dummy 322 Dummy 323 Dummy 324 Dummy 325 Dummy 326 Dummy 327 VSS 328 VSS 329 VSS 330 VSS 331 VSS 332 VS 333 VS 334 VS 335 VS 336 VS 337 VGD 338 VGD 339 VGD 340 VGD 341 VR 342 VR 343 VR 344 VR 345 VDC 346 VDC 347 VDC 348 VDC 349 VDC 350 VDC X [m] -6780.00 -6840.00 -6900.00 -6960.00 -7080.00 -7140.00 -7260.00 -7320.00 -7440.00 -7500.00 -7620.00 -7680.00 -7800.00 -7860.00 -7980.00 -8040.00 -8100.00 -8160.00 -8280.00 -8340.00 -8400.00 -8460.00 -8580.00 -8640.00 -8700.00 -8760.00 -8880.00 -8940.00 -9000.00 -9060.00 -9180.00 -9240.00 -9360.00 -9420.00 -9540.00 -9600.00 -9720.00 -9780.00 -9840.00 -10677.00 -10737.00 -10797.00 -10788.00 -10688.01 -10588.02 -9879.99 -9780.00 -9705.00 -9630.00 -9555.00 -9480.00 -9380.01 -9305.01 -9230.01 -9155.01 -9080.01 -8980.02 -8905.02 -8830.02 -8755.02 -8655.03 -8580.03 -8505.03 -8430.03 -8330.04 -8255.04 -8180.04 -8105.04 -8030.04 -7955.04 Y [m] 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 594.99 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 No. PAD Name 351 VDC 352 VDC2 353 VDC2 354 VDC2 355 VDC2 356 VDC2 357 VDC2 358 VDC2 359 C1+ 360 C1+ 361 C1+ 362 C1+ 363 C1+ 364 C1+ 365 C1+ 366 C1367 C1368 C1369 C1370 C1371 C1372 C1373 C2+ 374 C2+ 375 C2+ 376 C2+ 377 C2+ 378 C2+ 379 C2+ 380 C2381 C2382 C2383 C2384 C2385 C2386 C2387 C3+ 388 C3+ 389 C3+ 390 C3391 C3392 C3393 C4+ 394 C4+ 395 C4+ 396 C4397 C4398 C4399 C5+ 400 C5+ 401 C5+ 402 C5403 C5404 C5405 DCCLK 406 VDD2 407 VDD2 408 VSS1 409 VSS1 410 VSS2 411 VSS2 412 TEST_VCLAMP 413 TEST_VCLAMP 414 TEST_COM2 415 TEST_COM2 416 BGR_O 417 MVS 418 MVS 419 Dummy 420 Dummy X [m] -7880.04 -7780.05 -7705.05 -7630.05 -7555.05 -7480.05 -7405.05 -7330.05 -7230.06 -7155.06 -7080.06 -7005.06 -6930.06 -6855.06 -6780.06 -6680.07 -6605.07 -6530.07 -6455.07 -6380.07 -6305.07 -6230.07 -6130.08 -6055.08 -5980.08 -5905.08 -5830.08 -5755.08 -5680.08 -5580.09 -5505.09 -5430.09 -5355.09 -5280.09 -5205.09 -5130.09 -5030.10 -4955.10 -4880.10 -4780.11 -4705.11 -4630.11 -4530.12 -4455.12 -4380.12 -4280.13 -4205.13 -4130.13 -4030.14 -3955.14 -3880.14 -3780.15 -3705.15 -3630.15 -3530.16 -3430.17 -3355.17 -3255.18 -3180.18 -3080.19 -3005.19 -2905.20 -2830.20 -2730.21 -2655.21 -2555.22 -2455.23 -2380.23 -2280.24 -2180.25 Y [m] -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 No. PAD Name 421 Dummy 422 Dummy 423 Dummy 424 Dummy 425 Dummy 426 Dummy 427 VCC 428 VCC 429 VCC 430 VCC 431 VSS 432 VSS 433 VSS 434 VSS 435 VSS 436 STHR 437 GOE2_I 438 GOE1_I 439 GSTB_I 440 GCLK_I 441 STB 442 AP 443 POL 444 TCON 445 PVCC 446 OSEL 447 VCSEL 448 GAM 449 MAS/SLV 450 SCLEG1 451 SCLEG0 452 CKS 453 HSEG 454 VSEG 455 PVSS 456 EXT3_I 457 EXT2_I 458 EXT1_I 459 BSW_I 460 GSW_I 461 RSW_I 462 Dummy 463 Dummy 464 Dummy 465 Dummy 466 Dummy 467 /RESET 468 A0 469 CS2 470 CS1 471 SCLK_SUB 472 SOSUB 473 LCDCS 474 LCDCS 475 SCLK 476 SCLK 477 SI 478 SI 479 SO 480 SO 481 VSYNC 482 HSYNC 483 HSYNC 484 DCK 485 DCK 486 Dummy 487 Dummy 488 Dummy 489 Dummy 490 Dummy X [m] -2080.26 -1980.27 -1880.28 -1780.29 -1680.30 -1580.31 -1480.32 -1405.32 -1330.32 -1255.32 -1155.33 -1080.33 -1005.33 -930.33 -855.33 -755.34 -655.35 -555.36 -455.37 -355.38 -255.39 -155.40 -55.41 44.58 144.57 244.56 344.55 444.54 544.53 644.52 744.51 844.50 944.49 1044.48 1144.47 1244.46 1344.45 1444.44 1544.43 1644.42 1744.41 1844.40 1944.39 2044.38 2144.37 2244.36 2344.35 2444.34 2544.33 2644.32 2744.31 2844.30 2944.29 3019.29 3119.28 3194.28 3294.27 3369.27 3469.26 3544.26 3644.25 3744.24 3819.24 3919.23 3994.23 4094.22 4194.21 4294.20 4394.19 4494.18 Y [m] -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 No. 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 PAD Name D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHL STHL TESTOUT TESTIN4 TESTIN3 TESTIN2 TESTIN1 V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 Dummy Dummy Dummy Dummy Dummy Dummy Dummy COMDCSL COMDCIN COMDCIN VCOMH VCOMH VCOMH VCOMH COMDC COMDC COMC COMC COMC COMC COMC Dummy Dummy Dummy Dummy X [m] 4594.17 4694.16 4794.15 4894.14 4994.13 5094.12 5194.11 5294.10 5394.09 5494.08 5594.07 5694.06 5794.05 5894.04 5994.03 6094.02 6194.01 6294.00 6393.99 6468.99 6568.98 6668.97 6768.96 6868.95 6968.94 7068.93 7143.93 7243.92 7318.92 7418.91 7493.91 7593.90 7668.90 7768.89 7843.89 7943.88 8043.87 8143.86 8243.85 8343.84 8443.83 8543.82 8643.81 8743.80 8818.80 8918.79 8993.79 9068.79 9143.79 9243.78 9318.78 9418.77 9493.77 9568.77 9643.77 9718.77 9818.76 10588.02 10688.01 10788.00 Y [m] -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 -607.50 Preliminary Product Information S16269EJ2V0PM 5 PD161831 3. PIN FUNCTIONS 3.1 Source Driver Control Pins (1/2) Pin Symbol S1 to S244 Pin Name Driver output Pin Number 248 to 5 I/O OSEL = L: S1 to S244 OSEL = H: S3 to S242 OSEL Driver output count switching 446 Input The output count can be selected. When OSEL = H, the unused pins S1, S2, S243, S244 always become Hi-Z (high impedance). OSEL = L: 244 outputs OSEL = H: 240 outputs DCK CKS Dot clock Dot clock inversion 484, 485 452 Input Input Dot clock signal Inverts the active level of the dot clock. CKS = L: Low active CKS = H: High active HSYNC Horizontal sync signal 482, 483 Input Horizontal sync signal input pin. Do not input a width wider than the horizontal period as the width of the HSYNC active level. VSYNC HSEG Vertical sync signal HSYNC polarity selection 481 453 Input Input Vertical sync signal input pin. Selects the active level of the HSYNC signal. HSEG = L: Low active HSEG = H: High active VSEG VSYNC polarity selection 454 Input Selects the active level of the VSYNC signal. VSEG = L: Low active VSEG = H: High active D00 to D05 D10 to D15 D20 to D25 SCLK SO SI LCDCS SCLEG0, SCLEG1 VCSEL Serial clock input Serial data output Serial data input Serial clock mode selection COM amplitude output fixing signal Display data input 508 to 503 502 to 497 496 to 491 475, 476 479, 480 477, 478 451, 450 447 Input Input Input Input Input Input The display data is input with a width of 18 bits, the gray scale data (6 bits) by 3 dots (1 pixels). DX0: LSB, DX5: MSB Clock pin of serial interface. Data input pin of serial interface. Chip select pin of serial interface. Mode select pin of serial clock. For details, refer to 4. REGISTERS for explanation in serial interface . Fixes the VCOM output to L. When not using the VCOM output, set VCSEL to L. VCSEL = L: VCOM output fixed to L VCSEL = H: VCOM signal output in accordance with POL signal GAM External -usage selection 448 Input When the -correction power supply is input externally, switch GAM to H. If two or more chips are used, be sure to input the correction power supply externally. Figure 3-1 shows VCOM application example. GAM = L: External -correction power supply not input GAM = H: External -correction power supply input Description Output The D/A converted 64-gray-scale analog voltage is output. Output Data output pin of serial interface. Serial interface chip select 473, 474 6 Preliminary Product Information S16269EJ2V0PM PD161831 (2/2) Pin Symbol MAS, /SLV Pin Name Master slave control Pin Name 449 I/O Input Description When the timing generator is used and 2 chips are connected in cascade, selects use either as master IC or slave IC. When the timing generator is not used, either leave this pin or input a high level. MAS, /SLV = L: Use as slave MAS, /SLV = H: Use as master V0-V4 -corrected power supplies 525 to 516 Input These pins input the -corrected power supplies from outside, the relationship below must be observed. Also, be sure to stabilize the gray-scale-level power supply during gray-scale voltage output. VSS V4 V3 V2 V1 V0 VS VCOMH COMC COMDC COMDCIN COMDCSL TCON Amplitude voltage Square wave signal output 536 to 539 542 to 546 Output Output Output Input Input Input Outputs the voltage set with the amplitude voltage adjustment D/A converter. Outputs the square wave signal obtained through common modulation of Vp-p voltage 0 V-VCOMH. Outputs the common center voltage. Input pin used to input the common center voltage from external. Valid when COMDCSL = H. Inputs a H level as the common voltage when the voltage input from the COMDCIN pin is used. This pin is used to select whether or not to use the timing generator. TCON = L: Timing generator used TCON = H: Timing generator not used Common center voltage 540, 541 output Common center voltage 534, 535 external input Common center voltage 533 external input switch Timing generator use/non-use selection 444 /RESET Reset 467 Input Reset pin. This is the active low signal. Figure 3-1. VCOM Application Example - VS VS R-strings VS COMH (3:0) register 4 bit DAC R = 460 k to 920 k (1/50) VS step VCOMH [(34/50) VS to (49/50) VS] 4.7 F POL COMC COM VS 0.6 VS (V) COMDC COMM (6:0) register 7 bit DAC COMDCSL COMDCIN Preliminary Product Information S16269EJ2V0PM 7 PD161831 3.2 Gate Scan Control Pins Pin Symbol GCLK_O GSTB_O GOE1_O GOE2_O GCLK_I Pin Name Gate CLK output Gate STB output Gate OE1 output Gate OE2 output Gate CLK input Pin Name 315, 316 317, 318 311, 312 307 to 310 440 I/O Output Output Output Output Input Description Pin for CLK output to the gate control circuit. Pin for strobe signal fed to gate control circuit Pin for OE1 output to gate control circuit Pin for OE2 output to gate control circuit Input the CLK signal to the gate control circuit, when the timing generator function is not used. The signal input to this pin is output from the GCLK_O via a level shifter. Input the STB signal to the gate control circuit, when the timing generator function is not used. The signal input to this pin is output from the GSTB_O via a level shifter. Input the OE1 signal to the gate control circuit, when the timing generator function is not used. The signal input to this pin is output from the GOE1_O via a level shifter. Input the OE2 signal to the gate control circuit, when the timing generator function is not used. The signal input to this pin is output from the GOE2_O via a level shifter. Pin that outputs R,/L to the gate control circuit. GSTB_I Gate STB input 439 Input GOE1_I Gate OE1 input 438 Input GOE2_I Gate OE2 input 437 Input GR,/L_O Gate R,/L output 313, 314 Output 3.3 Control Pin for Multiplex Switch, etc. Pin Symbol RSW_O GSW_O BSW_O EXT1_O EXT2_O EXT3_O RSW_I Multiplex control signal input Extension control signal output Pin Name Multiplex control signal output Pin Name 287, 288 285, 286 283, 284 293, 294 291, 292 289, 290 461 I/O Output Output Output Output Output Output Input Pin for inputting the signal that controls the multiplex switch on the panel, when the timing generator function is not used. The signal input to this pin is output from the RSW_O pin via a level shifter. Pin for inputting the signal that controls the multiplex switch on the panel, when the timing generator function is not used. The signal input to this pin is output from the GSW_O pin via a level shifter. Pin for inputting the signal that controls the multiplex switch on the panel, when the timing generator function is not used. The signal input to this pin is output from the BSW_O pin via a level shifter. Pin for inputting the extension signal that controls the circuit on the panel, when the timing generator function is not used. The signal input to this pin is output from the EXT1_O pin via the level shifter. Pin for inputting the extension signal that controls the circuit on the panel, when the timing generator function is not used. The signal input to this pin is output from the EXT2_O pin via the level shifter. Pin for inputting the extension signal that controls the circuit on the panel, when the timing generator function is not used. The signal input to this pin is output from the EXT3_O pin via the level shifter. Extension output pin that controls the circuit on the panel. Description Output pin that controls the multiplex switch on the panel. GSW_I 460 Input BSW_I 459 Input EXT1_I Extension control signal input 458 Input EXT2_I 457 Input EXT3_I 456 Input 8 Preliminary Product Information S16269EJ2V0PM PD161831 3.4 Power Supply Function Control Pin Pin Symbol Pin Name Booster capacitor connection DC/DC converter output 352 to 358 - Pin Name 359 to 404 I/O - Description Connect the boost capacitor of the DC/DC converter to this pin. Booster ratio is difference on the way of using condenser connection. For details, refer to figure 3-3. DC/DC converter boost output (VDC x 2 or VDC x 3). This output is the VS and VR amplifier power supply. The VDC2 boot step is selected with the VCD2 bit. VCD2 bit = 0: VDC x 2 VCD2 bit = 1: VDC x 3 VS MVS Source power supply output External resistance input VR VDD2 VSS1 VSS2 VDC Reference power supply output DC/DC converter output DC/DC converter output DC/DC converter output Reference power supply input for source power supply voltage VGD Reference power supply input for gate power supply voltage DCCLK Boost clock input 405 Input Pin used to input boost clock of DC/DC converter. 337 to 340 - Extension pin used to control circuit on panel. 345 to 351 - Extension pin used to control circuit on panel. 303 to 306, 406, 407 299 to 302, 408 to 411 295 to 298 - DC/DC converter boost output (VGD x -2) - DC/DC converter boost output (VGD x -1) - 341 to 344 - 417, 418 Input 336 to 332 - Source voltage output pin. The VS output voltage can be changed through the VSEL0 to VSEL2. An external resistance can be input to set any output voltage. EXRV bit = 0: Leave open (Internal resistor selection) EXRV bit = 1: Connect external resistor. Gate reference power supply output pin. The VR output voltage can be changed through the VRSEL to VRSEL2 setting. DC/DC converter boost output (VGD x 2) 5 C1+/-,C2+/-, C3+/-,C4+/-, C5+/- VDC2 Figure 3-2. DC/DC Converter Boost Configuration - VDD2: VR x 2 or VS x 2 VDC2: VDC x 2 or VDC x 3 VCC: 2.5 to 3.6 V VDC: 2.5 to 3.6 V VSS: 0 V VR, VS VSS1: VR x -1 or VS x -1 Regulator outputs VR and VS are generated from VDC2. The following voltages can be selected for VS and VR. 3.0 V, 3.5 V, 4.0 V, 4.5 V, 4.75 V, 5.0 V, 5.25 V, 5.5 V VSS2: VR x -2 or VS x -2 Preliminary Product Information S16269EJ2V0PM 9 PD161831 5 Figure 3-3. Relationship between Condenser Connection for Booster and Booster Ratio - VDC2 = VDC x 2 (dual mode) C1+ VDD2 C1C2+ C2VDD2 VDC2 = VDC x 2 (single mode) C1+ C1C2+ C2VDD2 VDC2 = VDC x 3 C1+ C1C2+ C2- VDD2 = VGD x 3 VSS1 = VGD x -2 VSS2 = VGD x -3 C3+ C3C4+ C4C5+ C5VSS2 VSS1 VDD1 VDD2 = VGD x 3 VSS1 = - VSS2 = VGD x -2 C3+ C3C4+ C4C5+ C5VSS2 VSS1 VDD1 VDD2 = VGD x 2 VSS1 = VGD x -1 VSS2 = VGD x -2 C3+ C3C4+ C4C5+ C5VSS2 VSS1 VDD1 VDD2 = VGD x 2 VSS1 = - VSS2 = VGD x -1 C3+ C3C4+ C4C5+ C5VSS2 VSS1 VDD1 Figure 3-4. VS, Amp. Circuit Configuration - TESTOUT1 VDC2 TESTOUT1 VDC2 VREF MVS - C3 VREF MVS 4 V, 5 V C3 RbS RaS - C3 + RbS RcS RaS + VS 4 V, 5 V C3 Internal Resistor Mode EXRV = L External Resistor Mode EXRV = H RbS VS =(1+ )VREF RaS 10 Preliminary Product Information S16269EJ2V0PM PD161831 3.5 Control Pins when Timing Generator Function Not Used, and Other Pins Pin Symbol STHR STHL STB Pin Name Right shift start pulse I/O Left shift start pulse I/O Latch input 441 Input 509, 510 I/O Pin Name 436 I/O I/O Description Start pulse I/O pin during cascade connection. When an H level is read at the rising edge of CLK, fetching of display data starts. In the case of right shift, STHR = input and STHL = output. In the case of left shift, STHL = input and STHR = output. This is the timing signal at which the contents of the data register are latched. When an H level is read at the rising edge of CLK, the contents of the data register are latched and transferred to the D/A converter, and an analog voltage is output according to the display data. Even after STB fetch, do not stop CLK because the internal operation is performed using CLK. At the rising edge of STB, the content of the shift register are cleared. After one pulse is input at startup, the operation becomes normal. At the rising edge of STB, the output switch is switched OFF. For the STB input timing, refer to 5. TIMING GENERATOR NON-USE FUNCTION. AP Output SW ON/OFF 442 Input Switches the BIAS circuit ON/OFF and the output switch and amplifier ON. The period during which AP is H is the amplifier circuit setting period and the liquid crystal drive period. At the falling edge of AP, the amplifier output and output switch go ON and liquid crystal driving starts. At the rising edge of STB, the output switch is switched to OFF ad the output becomes Hi-Z. POL Polarity inversion signal 443 Input Inverts the output polarity. At the siring edge of RSEL, the polarity inversion signal data is fetched internally. The -resistor is switched according to the positive and negative polarity. POL = L: Negative polarity (common high output) POL = H: Positive polarity (common low output) 3.6 Back Panel LCD Controller Driver Control Pins Pin Symbol /CS1 Pin Name Back panel LCD chip select CS2 Back panel LCD chip select SCLK_SUB Serial clock to the back panel LCD SO_SUB Outputs serial data to the back panel LCD A0 Back panel LCD data/command control 468 Output Controls data/command to the back panel LCD controller driver. 472 Output Outputs serial data to the back panel LCD controller driver. 471 Output Back panel LCD serial data output. 469 Output Active-high chip select signal to the back panel LCD controller driver. Pin Name 470 I/O Output Description Active-low chip select signal to the back panel LCD controller driver. Preliminary Product Information S16269EJ2V0PM 11 PD161831 3.7 Other Control Pins Pin Symbol TESTIN1 to TESTIN4 TESTOUT TEST_COM2 TEST_VCLAMP Pin Name TEST input TEST output TEST output TEST output Hand cap regulator output Power supply for pull-up Power supply for pull-down Logic supply voltage Driver ground Dummy Pin Name 515 to 512 511 414, 415 412, 413 416 445 456 427 to 430 327 to 331. 431 to 435 I/O Input Output Output Output Output - - - - - Description Keep this pin low-level or leave it open. Leave this pin open. Leave this pin open. Leave this pin open. Leave this pin open. This is pull-up power supply for mode setting pin. This is pull-down power supply for mode setting pin. 2.2 to 3.6 V Grounding Dummy pin 5 5 5 BGR_O PVCC PVSS VCC VSS Dummy 1 to 4, 249 to 282, 319 to 326, 419 to 426, 462 to 466, 486 to 490, 526 to 532 Caution To avoid latch-up failure, the sequence when turning on the power must be VCC logic input booster voltage for rising gray-scale power supply (V0-V4), and the reverse sequence when turning off the power. Follow this sequence during shift periods as well. 12 Preliminary Product Information S16269EJ2V0PM PD161831 4. REGISTERS The PD161831 can set a horizontal period and vertical period by using registers. The serial interface is used to specify a register and set values to it. Figure 4-1 shows a simplified timing chart of the serial interface. Figure 4-1. Timing Chart of Serial Interface - LCDCS SCLK SI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Serial interface operation specification transfer - Specification of register - Specification of read or write - Selection of back panel LCD function - Selection of serial interface for gate Command & data transfer - Selection of command register - Transfer of set values of command register This serial interface has an 8-bit configuration. Note that it is accessed twice in 8-bit units to set a register. The first 8-bit data (A7 to A0 in figure 4-1) is transferred to the "serial interface operation specification register". The serial interface operation specification register specifies the transfer operation of the next 8 bits (D7 to D0 in figure 4-1). The second 8-bit data selects a command register or transfers the set value of the command register. In addition, while writing a setup in command register with the 8-bit transfer + 8-bit (A7 to A0 + D7 to D0) which selects command register or transferring of 8 bit + 8-bit transfer of readings (A7 to A0 + D7 to D0) (a total of 32 bits), continue making chip select (LCDCS) active. Table 4-1 indicates the function of the serial interface operation specification register. Table 4-2 shows the register number and register name of each command register. Tables 4-3 and 4-5 to 4-24 describe the function of each command register. When the timing generator is used, there are three execution patterns for each command: Immediate execution following setting, execution at the line following that where command was set, and execution at the frame following that where command was set. In the case of execution at the next line and execution at the next frame, the concrete command execution timing is as follows. However, when the timing generator is not used, commands are executed at the first falling edge of DCK following command transmission. Execution from next line following command input (HSYNC, DOTCLK = low active) <1> <2> <3> <4> DOTCLK HSYNC Command input in above interval is executed at the next line. <1> <2> <3> <4> DOTCLK Command execution Execution from next frame following command input (VSYNC, HSYNC, DOTCLK = low active) <1> <2> <3> <4> DOTCLK HSYNC VSYNC DOTCLK <1> <2> <3> <4> Command input in above interval is executed at the next line. Command execution Preliminary Product Information S16269EJ2V0PM 13 PD161831 4.1 Serial Interface Operation Specification Register Table 4-1 shows the function of the serial interface operation specification register. Table 4-1. Function of Serial Interface Operation Specification Register (A7 to A0) - No. A7 A6 - Bit Name - This bit specifies whether data D7 to D0 are data for a register of the PD161831 or data for the back panel LCD. If D7 to D0 are data for the back panel LCD, the chip select pins for the back panel LCD (/CS1 = L, CS2 = H) are asserted, and data D7 to D0 are output to SUB_SO along with the clock output by SCLK_SUB. 0: D7 to D0 are data for a PD161831 register. 1: D7 to D0 are data for the back panel LCD controller driver. A5 Read/write select This bit selects whether the transfer of data D7 to D0 is for a read operation or a write operation. Note, however, that in a read operation, only the registers of the PD161831 can be read. For the timing chart of the read operation, refer to 5. TIMING GENERATOR NON-USE FUNCTION. 0: D7 to D0 are for a write operation. 1: D7 to D0 are for a read operation. A4 A3 A2 A1 A0 - - - - Command/data select - - - - This bit selects whether data D7 to D0 specify the register number of a command register or are set to a command register. If an access to the back panel LCD controller driver is selected (A6 = 1), the value of this bit is reflected on the A0 pin (when A0 = 0: Low output, when A0 = 1: High output). 0: D7 to D0 specify a register number. 1: D7 to D0 are set to a register. Function PD161831/back panel LCD select 14 Preliminary Product Information S16269EJ2V0PM PD161831 4.2 Command Registers 4.2.1 Command register list Table 4-2 lists the command registers. However, each register is read default value when invalid data leads in unused of timing generator. Table 4-2. Command Register List (1/2) - Register No. R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13, R14 R15 R16 to R23 R24 R25 R26 R27 R28 R29 to R32 R33 R34, R35 D5 0 0 0 0 0 0 0 - 0 0 0 0 0 - 0 - 0 0 0 0 0 - 1 - D4 0 0 0 0 0 0 0 - 0 0 0 0 0 - 0 - 1 1 1 1 1 - 0 - D5 to D0 D3 0 0 0 0 0 0 0 - 1 1 1 1 1 - 1 - 1 1 1 1 1 - 0 - D2 0 0 0 0 1 1 1 - 0 0 0 1 1 - 1 - 0 0 0 0 1 - 0 - D1 0 0 1 1 0 0 1 - 0 0 1 0 0 - 1 - 0 0 1 1 0 - 0 - D0 0 1 0 1 0 1 0 - 0 1 1 0 1 - 1 - 0 1 0 1 0 - 1 - 65,000/260,000 color select Horizontal period valid data input start timing Vertical period valid data input start timing Horizontal valid pixel data setting Standby 8-color mode Setting Use prohibited (Not used) Amplifier drive period setting Quarter data function Level shifter voltage setting Common amplitude voltage adjustment D/A converter Common center voltage adjustment D/A converter Use prohibited (Not used) Command reset Use prohibited (Not used) DC/DC operation setting DC/DC step setting DC/DC oscillation setting Regulator output setting LPM setting Use prohibited (Not used) DC/DC rise setting Use prohibited (Not used) Default Value 00H 0AH 02H 00H 00H 00H 02H - 0EH 00H 00H 0FH 35H - 00H - 00H 16H 15H 2AH 00H - 00H - Timing Generator Function Register Name Reset Hard Internal Set Timing Use O O O O O O O - O O O O O - O - O O O O O - O - Not used Command - - - - O O 1 - - O O O O - O - O O O O O - O - O O O O O O O - O O O O O - - - O O O O O - O - - - - - - - Note1 - - - - - - - - - O O O O O - O - F F F C F L Note2 - C F C C C - C - C C C C C - C - Remarks 1. O: Enabled, -: Disabled, 1: Only bit 3 disabled, 2: Only bit 7 enabled 2. The internal set timing is the timing at which the command is enabled. C: Enabled when command is set F: Enabled at beginning of frame L: Enabled at beginning of line Notes 1. Bit 0 is enabled when line is set. Bit 3 is enabled when frame is set. Al other bits are enabled when command is set. 2. Bits 4 and 5 are enabled when hard reset is performed. All other bits are disabled. Preliminary Product Information S16269EJ2V0PM 15 PD161831 Table 4-2. Command Register List (2/2) - Register No. R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52, R53 R54 R55 R56 to R255 D5 to D0 D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 - D4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 - 1 1 - D3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 - 0 0 - D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 - 1 1 - D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 - 1 1 - D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - 0 1 - Register Name Default Value 0FH 1DH 1EH 2CH 2DH 3BH 0AH 0AH 0AH 0AH 0AH 0AH 80H 04H 38H 00H - 00H 00H - Timing Generator Function Reset Hard Internal Set Timing Use O O O O O O O O O O O O O O O O - O O - Not used Command - - - - - - - - - - - - 2 - - - - O O - O O O O O O O O O O O O O O O O - O O - RSW_O start timing setting RSW_O end timing setting GSW_O start timing setting GSW_O end timing setting BSW_O start timing setting BSW_O end timing setting EXT1_O start timing setting EXT1_O end timing setting EXT2_O start timing setting EXT2_O end timing setting EXT3_O start timing setting EXT3_O end timing setting EXT1 to EXT3 function setting GOE1 start timing setting GOE1 end timing setting Dummy line setting Use prohibited (Not used) COM2, VCLAMP control Test mode setting Use prohibited (Not used) - - - - - - - - - - - - - - - - - O - - C C C C C C C C C C C C C C C F - C C - Remarks 1. O: Enabled, -: Disabled, 1: Only bit 3 disabled, 2: Only bit 7 enabled 2. The internal set timing is the timing at which the command is enabled. C: Enabled when command is set F: Enabled at beginning of frame L: Enabled at beginning of line Notes 1. Bit 0 is enabled when line is set. Bit 3 is enabled when frame is set. Al other bits are enabled when command is set. 2. Bits 4 and 5 are enabled when hard reset is performed. All other bits are disabled. 16 Preliminary Product Information S16269EJ2V0PM PD161831 4.2.2 65,536/262,144 color select register This register is used to select the number of colors (65,536 or 262,144 colors) of one pixel and specify the data transfer mode when 262,144 colors are selected. If transferring 262,144 colors twice is selected, the time required to transfer the data of one pixel is two times longer than that of the first transfer (if the dot clock frequency is the same). To make the frame frequency for the first transfer and the second transfer the same, therefore, increase the dot clock frequency for the second transfer to twice that of the first transfer. Note also that the setting of this register is reflected from the operation of the next frame after the register is set. Table 4-3. 65,536/262,144 Color Select Register (R0) - Register Set Value 00H 01H 02H Note Note Function 65,536 colors: 16-bit data is transferred once 262,144 colors: 12-bit and 6-bit data are transferred twice. 262,144 colors: 9-bit and 9-bit data are transferred twice. 262,144 colors: 18-bit data is transferred once Use prohibited 03H 04H-FFH Note The 65,536/262,144 color select register cannot be used in mode that do not use the timing generator. The relationship between each data transfer mode and the display data input pins (D05 to D00, D15 to D10, and D25 to D20) is shown in the table below. The data input to D05 to D00 is output during the period while BSW_O is active, and the data input to D25 to D20 is output during the period while RSW_O is active. However, Red5, Green5, Blue5 in table 4-4 are the data lines needed to input in 8-color mode. Table 4-4. Relationship Between Data Transfer Mode and Display Data Input Pins ("-" indicates that input - - data is invalid) 262,144 Colors Display Data Input Pin D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 65,536 Colors One transfer, 18-bit Red5 Red4 Red3 Red2 Red1 Red0 Green5 Green4 Green3 Green2 Green1 Green0 Blue5 Blue4 Blue3 Blue2 Blue1 Blue0 Two transfers, 12-bit + 6-bit First transfer Red5 Red4 Red3 Red2 Red1 Second transfer Blue5 Blue4 Blue3 Blue2 Blue1 Two transfers, 9-bit + 9-bit First transfer Red5 Red4 Red3 Red2 Red1 Second transfer Green2 Green1 Green0 Blue5 Blue4 Red5 Red4 Red3 Red2 Red1 - Note - Red0 - Blue0 - Red0 Green5 Green4 Green3 - Blue3 Blue2 Blue1 Blue0 Green5 Green4 Green3 Green2 Green1 Green0 Blue5 Blue4 Blue3 Blue2 Blue1 - - Green5 Green4 Green3 Green2 Green1 Green0 - Note - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Note It is not necessary to input data to the D20 and D00 pins when 65,536 colors are selected, but amplifier output is performed on the assumption that data input to D25 and D05 is input to D20 and D00. 17 Preliminary Product Information S16269EJ2V0PM PD161831 4.2.3 Horizontal period valid input start timing setting register This register sets the timing to start inputting the valid data of the horizontal period in HSYNC and VSYNC mode. It sets the number of dot clocks from the falling edge of the HSYNC signal until the input data becomes valid. If transferring display data twice is selected, set half the number of dot clocks actually needed. Note also that the setting of this register is reflected from the operation of the next frame after the register is set. Table 4-5. Horizontal Period Valid Input Start Timing Setting Register (R1) - Register Set Value 00H 01H : 04H 05H 06H 07H : FDH FEH FFH Number of Dot Clocks 4 clocks 4 clocks : 4 clocks 5 clocks 6 clocks 7 clocks : 253 clocks 254 clocks 255 clocks 4.2.4 Vertical period valid input start timing setting register This register sets the timing to start inputting the valid data of the vertical period in HSYNC and VSYNC mode. It sets the number of HSYNC from the falling edge of the VSYNC signal until the input data becomes valid. Note also that the setting of this register is reflected from the operation of the next frame after the register is set. Table 4-6. Vertical Period Valid Input Start Timing Setting Register (R2) - Register Set Value 00H 01H 02H 03H 04H 05H 06H : FDH FEH FFH Number of HSYNC Signals 2 2 2 3 4 5 6 : 253 254 255 18 Preliminary Product Information S16269EJ2V0PM PD161831 4.2.5 Horizontal Valid Pixel Data Register This register sets the number of valid pixel data during the horizontal period in HSYNC and VSYNC mode. Note also that the setting of this register is reflected from the operation of the next frame after the register is set. Table 4-7. Horizontal Valid Pixel Data Register (R3) - Register Set Value 00H 01H 02H 03H Number of Valid Data 240 244 480 488 4.2.6 Standby register This register is used to set or restore from a standby mode. The data set to bits 7 to 1 of this register is ignored. When a standby command is input, the PD161831 performs white display (source output, and VSS level output by COMC) from the next frame following command output. Following the execution of this command, execute the regulator OFF command and the DC/DC converter OFF for the power supply function. Also when standby is canceled, doing the opposite of when standby is input, execute the normal operation command (R4 = "0") after setting both the DC/DC converter and the regulator to ON.. Table 4-8. Standby Register (R4) - Bit 0 Set Value 0 1 Mode Normal operation mode Standby mode 4.2.7 8-color mode register This register is used to select the 8-color mode. The data set to bits 7 to 1 of this register is ignored. The data line that must be input in 8-color mode differs depending on the selection of the 65,000-color mode and 260,000-color transfer mode. For the actual data line to be used, refer to Table 4-4. Note that the setting of this register is reflected from the operation of the next line after the register is set. Table 4-9. 8-Color Mode Register (R5) - Bit 0 Set Value 0 1 Mode 65,000/260,000 colors (R0 register is valid) 8-color mode Preliminary Product Information S16269EJ2V0PM 19 PD161831 4.2.8 Setting register This register is used to set the low power mode and the direction of scanning. Data set to bits 6 and bit7 of these register are ignored. Table 4-10. Setting Register (R6) - Bit Name Bit 0 Mode Adjusts the driver bias current of the PD161831 to enter the low power mode. Since the through rate of the operational amplifier inside the IC changes, be sure to carefully perform panel evaluation. Note that the setting of this bit is reflected from the operation of the next line after the register values are set. Bit 0 = 0: Driver output low power mode Bit 0 = 1: Normal mode Bit 1 Selects the scanning direction by using the GRL_O and GSTB_O pins. This bit becomes valid as soon as it is set. Therefore, it must be set after gate scanning of one frame has been completed and before scanning of the next frame is started. The setting of this bit is reflected in the operation immediately after the register is set. Bit 1 = 0: Reverse scan (scanning from bottom to top, GRL_O = L output) Bit 1 = 1: Forward scan (scanning from top to bottom, GRL_O = H output) Bit 2 Selects whether the display data input to the PD161831 is input from S3 to S242, or vice versa. <240 output selection> Bit2 = 0: S242 S3 Bit2 = 1: S3 S242 <244 output selection> Bit2 = 0: S244 S1 Bit2 = 1: S1 S244 The relationship between the input data and output pin is as follows: The setting of this bit is reflected in the operation immediately after the register is set. Bit 3 Selects whether the line or frame is inverted. In the 8-color mode, the power consumption can be further reduced by selecting frame inversion. The setting of this bit is reflected from the operation of the next line after the register is set. Bit 3 = 0: Line inversion Bit 3 = 1: Frame inversion Bit 4 Performs GOE1 output control. When bit 4 = 0, a Low level is forcibly output to GOE1. Bit 4 = 0: Forcible output of low level to GOE1. Bit 4 = 1: Normal operation Bit 5 Controls ON/OFF switching of square wave output from the COMC pin. Bit 5 = 0: Output VSS level Bit 5 = 1: Output square wave Bit 6, bit 7 Use prohibited 20 Preliminary Product Information S16269EJ2V0PM PD161831 4.2.9 Amplifier drive period setting register In the PD161831, the amplifier drive period is set with the horizontal period address count (HCNT) as the driver output. The amplifier drive period set with this register is the drive period of R, G, and B, respectively, when division by 3 is performed. The amplifier drive start timing is the RGW_O, GSW_O, and BSW_O signal start timing. For detail, refer to figures 4-2 through 4-6. Note that the setting of this register is reflected to the operation immediately after the register is set. The effective bits of this register are bit 0 to bit 4. Figure 4-7 indicates how the amplifier of the PD161831 is driven. Table 4-11. Amplifier Drive Period Setting Register (R8) - Register Set Value 00H 01H 02H 03H 04H : 1DH 1EH 1FH Horizontal Period Address Count 0 1 2 3 4 : 29 30 31 Preliminary Product Information S16269EJ2V0PM 21 PD161831 Figure 4-2. Horizontal Period Amplifier Drive Timing and GCK/GOE1 Signal Output Timing - (When line inversion is set: When VSYNC signal is active) PD161831 display timing chart HSYNC VSYNC CLK 56 57 58 59 - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 HCNT It is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by R1 register. The address count of a level period starts after level effective data input start timing. over 1.0 s MIN. GCLK_O GSTB_O GOST [5:0] GOE1_O GOED [5:0] A setup which does not generate a pulse is prohibited about GOE1 (prohibition of this address value setup about a start and a stop). GOE2_O RSW_O RST [5:0] GST [5:0] RED [5:0] GED [5:0] GSW_O BST [5:0] BSW_O BED [5:0] E1ST [5:0] EXT1_O E1ED [5:0] E2ST [5:0] EXT2_O E2ED [5:0] E1ST [5:0] EXT3_O E1ED [5:0] resistance direct driving period R8 amplifier driving period R8 amplifier driving period resistance direct driving period R8 amplifier driving period resistance direct driving period Y1 to Y240 Hi-Z R output G output B output Hi-Z R output COMC Gn OUT Gn+1 OUT 22 Preliminary Product Information S16269EJ2V0PM PD161831 Figure 4-3. Horizontal Period Amplifier Drive Timing and GCK/GOE1 Signal Output Timing - (When line inversion is set: Line immediately after VSYNC to valid data input start line) PD161831 display timing chart Line right after VSYNC to valid data input start ling HSYNC VSYNC CLK 56 57 58 59 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 54 HCNT It is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by R1 register. The address count of a level period starts after level effective data input start timing. over 1.0 s MIN. GCLK_O GSTB_O GOST [5:0] GOED [5:0] GOE1_O A setup which does not generate a pulse is prohibited about GOE1 (prohibition of this address value setup about a start and a stop). GOE2_O RSW_O RST [5:0] GST [5:0] RED [5:0] GED [5:0] GSW_O BST [5:0] BSW_O BED [5:0] E1ST [5:0] EXT1_O E1ED [5:0] E2ST [5:0] EXT2_O E2ED [5:0] E1ST [5:0] R8 amplifier driving period EXT3_O E1ED [5:0] resistance direct driving period R8 amplifier driving period resistance direct driving period R8 amplifier driving period resistance direct driving period Y1 to Y240 Hi-Z R output G output B output Hi-Z R output COMC Gn OUT Gn+1 OUT HSYNC DOTCLK 16 CLK CLK HCNT - - - - - 0 1 Preliminary Product Information S16269EJ2V0PM 23 PD161831 Figure 4-4. Horizontal Period Amplifier Drive Timing and GCK/GOE1 Signal Output Timing - (When line inversion is set: Laid data input start line to GSTB output line) PD161831 display timing chart Valid data input start line and next line (G output) STB Valid data input start line HSYNC VSYNC CLK 56 57 58 59 - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 HCNT It is a tim chart at the tim of using level period effective data input start timing as a 16-dot clock by R1 register. ing e The address count of a level period starts after level effective data input start timing. over 1.0 s M IN. GCLK_O GSTB_O GSTB output GO [5:0] ST GO [5:0] ED GOE1_O A setup which does not generate a pulse is prohibited about GOE1 (prohibition of this address value setup about a start and a stop). GOE2_O RED [5:0] RSW_O RST [5:0] GST [5:0] GED[5:0] GSW_O BST [5:0] BSW_O BED [5:0] E1ST [5:0] EXT1_O E1ED [5:0] E2ST [5:0] EXT2_O E2ED [5:0] E1ST [5:0] EXT3_O E1ED [5:0] resistance direct driving period R8 amplifier driving period R8 amplifier driving period resistance direct driving period R8 amplifier driving period resistance direct driving period Y1 to Y240 Hi-Z R output Goutput B output Hi-Z R output G COMC Gn OUT Gn+1 OUT 24 Preliminary Product Information S16269EJ2V0PM PD161831 Figure 4-5. Horizontal Period Amplifier Drive Timing and GCK/GOE1 Signal Output Timing - (When frame inversion is set, positive polarity) PD161831 display timing chart (frame inversion/positive polarity, 240 output) Display CLK address value (HCNT) is four times cycling in DOTCLK Display CLK address value (HCNT) can be set up to 1-58 (0, 59, and 59 or more addresses prohibited). When all 240 or more CLK are put in 1H period, it is added after display CLK address value (HCNT) 58 HSYNC VSYNC CLK 56 57 58 59 - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 HCNT It is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by R1 register. The address count of a level period starts after level effective data input start timing. over 1.0 s M IN. GCLK_O GSTB_O GOST [5:0] GOED [5:0] GOE1_O A setup which does not generate a pulse is prohibited about GOE1 (prohibition of this address value setup about a start and a stop). GOE2_O RED [5:0] RSW_O RST [5:0] GST [5:0] GED [5:0] GSW_O BSW_O E1ST [5:0] EXT1_O E1ED [5:0] E2ST [5:0] EXT2_O E2ED [5:0] E1ST [5:0] EXT3_O E1ED [5:0] BST [5:0] BED [5:0] resistance direct driving period R8 amplifier driving period R8 amplifier driving period resistance direct driving period R8 amplifier driving period resistance direct driving period Y1 to Y240 Hi-Z R output G output B output Hi-Z R output COMC Gn OUT Gn+1 OUT Preliminary Product Information S16269EJ2V0PM 25 PD161831 Figure 4-6. Horizontal Period Amplifier Drive Timing and GCK/GOE1 Signal Output Timing - (When frame inversion is set, negative polarity) PD161831 display tim chart (fram inversion/negatibe polarity, 240 output) ing e Display CLKaddress value (HCNT) is four tim cycling in DO es TCLK Display CLKaddress value (HCNT) can be set up to 1-58 (0, 59, and 59 or m addresses prohibited). ore W all 240 or m CLK are put in 1Hperiod, it is added after display CLK address value (HCNT) 58 address. hen ore HSYNC VSYNC CLK 56 57 58 59 - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 HCNT It is a tim chart at the tim of using level period effective data input start tim as a 16-dot clock by R1 register. ing e ing The address count of a level period starts after level effective data input start timing. over 1.0 s M IN. G CLK_O G STB_O G ST [5:0] O G ED [5:0] O G OE1_O A setup which does not generate a pulse is prohibited about G E1 (prohibition of this address O value setup about a start and a stop). G OE2_O RSW _O RST [5:0] G [5:0] ST RED[5:0] G [5:0] ED G _O SW BSW _O E1ST [5:0] EXT1_O E1ED[5:0] E2ST [5:0] EXT2_O E2ED[5:0] E1ST [5:0] EXT3_O E1ED[5:0] BST [5:0] BED [5:0] resistance direct driving period R8 amplifier driving period R8 amplifier driving period resistance direct driving period R8 am plifier driving period resistance direct driving period Y1 to Y240 Hi-Z Routput Goutput B output Hi-Z Routput CO C M G OUT n G OUT n+1 26 Preliminary Product Information S16269EJ2V0PM PD161831 The LCD driver circuit of the PD161831 consists of " resistor", " select switch", "D/A converter", and "output stage", as shown below. The following amplifier drive period can be selected by using R8, the amplifier drive period setting register. resistor : String resistor for curve select switch: Selects curve during positive pole or negative pole driving D/A converter : Selects the output voltage level from display data. Output stage : Consists of a driving amplifier, a switch for voltage hold driving, and an inverter for 8-color display. Figure 4-7. Output circuit image of Amplifier Drive Operation - selction SW V0 Positive polarity Negative polarity DAC SW OUT Amp. Output for 8-color display V4 Preliminary Product Information S16269EJ2V0PM 27 PD161831 4.2.10 Quarter data function register The quarter data function is selected with the bit 0 setting. Table 4-12. Quarter Data Function Register (R9) - Bit 0 0 1 Mode Normal operation Quarter data function operation When the quarter data function is selected, one pixel of input data is also used as the neighboring 1 pixel of data. The data that is next input externally becomes the pixel data after the neighboring 1-pixel data mentioned above. Figure 4-8. Quarter Data Function - Driver output S1 Driver output S2 Driver output S3 Driver output S4 Driver output S5 Driver output S1 Driver output S2 Driver output S3 Driver output S4 Driver output S5 28 Preliminary Product Information S16269EJ2V0PM PD161831 Moreover, when the quarter data function is selected, 2-lines' worth of data output are gate scanned during the horizontal period corresponding to 1 line. Figure 4-9. Gate Scan Operation when Quarter Data Function is Selected - Normal operation mode (gate scan performed once during 1 horizontal period) Quarter data function mode (gate scan performed twice during 1 horizontal period) HSYNC HSYNC The horizontal period timing is as follows. Gate scan Gate scan Preliminary Product Information S16269EJ2V0PM 29 PD161831 Figure 4-10. Horizontal Period Timing Chart when Quarter Data Function is Selected - PD161831 display tim chart (line inversion, 240 output, quarter data function) ing Display CLK address value (HCNT) is four times cycling in DOTCLK Display CLK address value (HCNT) can be set up to 1-58 (0, 59, and 59 or more addresses prohibited). When all 240 or more CLK are put in 1H period, it is added after display CLK address value (HCNT) 58 address. HSYNC VSYNC After HSYNC becomes active, a level period starts by 1 clock of DOTCLK. DOTCLK 56 57 58 59 - - - - - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 - - - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 HCNT It is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by R1 register. The address count of a level period starts after level effective data input start timing. over 1.0 s M IN. GCLK_O It is a tim chart at the tim of using level period effective data input ing e start tim as a 16-dot clock by R1 register. The address count of a ing level period starts after level effective data input start timing. over 1.0 ms M IN. After HSYNC becomes active, GCLK becomes active by 2 clock of DOTCLK. GSTB_O GOST [5:0] GOE1_O GOED [5:0] A setup which does not generate a pulse is prohibited about GOE1 (prohibition of this address value setup about a start and a stop). GOE2_O RSW_O RST [5:0] GST [5:0] RED [5:0] GED [5:0] GSW _O BSW_O E1ST [5:0] EXT1_O E1ED [5:0] E2ST [5:0] EXT2_O E2ED[5:0] E1ST [5:0] EXT3_O E1ED[5:0] BST [5:0] BED [5:0] resistance direct driving period R8 amplifier driving period R8 amplifier driving period resistance direct driving period R8 amplifier driving period resistance direct driving period Y1 to Y240 Hi-Z R output G output B output Hi-Z R output COMC Gn OUT Gn+1 OUT 30 Preliminary Product Information S16269EJ2V0PM PD161831 As an image, in order to perform display of 240 outputs x 320 lines during normal operation, 240 outputs x 640 lines of data are input, but when the quarter data function is selected, in order to perform display of 240 outputs x 320 lines, just 120 outputs x 160 lines of data can be input. While display is less fine compared to during normal operation, the input data is just one fourth the amount during normal operation, and transfer data can be reduced during moving picture display. Panel size 240 outputs x 320 lines 4.2.11 Level shifter voltage setting register Then negative voltage level of the level shifter is set by setting bit 0 and bit1. The circuit block of the level shifter is divided into the gate control signal side (GCLK_O, GSTB_O, GOE1_O, GOE2_O) and the driver output related signal side (RSW_O, GSW_O, BSW_O, EXT1_O to EXT3_O), and the negative voltage side voltage level can be selected individually for the gate control signal side and the driver output related signal side between either VSS1 and VSS2 with the R11 register. The data set to bit 1 and bit 2 is ignored. Note that the setting of this register is reflected to the operation immediately after the register is set. Table 4-13. Level Shifter Voltage Setting Register (R10) - Bit Name Bit 0 Mode Sets the voltage level on the negative voltage side of the gate output control signals (GCLK_O, GSTB_O, GOE1_O, GOE2_O). Bit 0 = 0: VSS2 level Bit 0 = 1: VSS1 level Bit 1 Sets the voltage level on the negative voltage side of the driver output related signals (RSW_O, GSW_O, BSW_O, EXT1_O to EXT3_O) Bit 1 = 0: VSS2 level Bit 1 = 1: VSS1 level Preliminary Product Information S16269EJ2V0PM 31 PD161831 4.2.12 Common amplitude voltage adjustment D/A converter register The common amplitude voltage can be selected by setting bit 0 to bit 3 of the R11 register. The voltage between (34/50)*VS and (49/50)*VS is divided by the 4-bit D/A converter. Note that the setting of this register is reflected to the operation immediately after the register is set. 4.2.13 Common center voltage adjustment D/A converter register The common center voltage can be selected by setting bit 0 to bit 6 of the R12 register. The voltage between 0 (V) and 0.6*VS (V) is divided by the 7-bit D/A converter. Note that the setting of this register is reflected to the operation immediately after the register is set. 4.2.14 Command reset register Bit 0 of this register is used to initialize the command register. Data set to bit 1 to bit 7 is ignored. Command reset is automatically cleared after it is set. The setting of this bit is reflected in the operation immediately after the register is set. Table 4-14. Command Reset Register (R15) - Bit 0 0 1 Mode Normal operation Command reset 4.2.15 DC/DC operation setting register The register is used to switch ON/OFF the DC/DC converter controls and switch ON/OFF boosting of each power supply. Table 4-15. DC/DC Operation Setting Register (R24) - Bit Name Bit 0 32 Preliminary Product Information S16269EJ2V0PM PD161831 4.2.16 DC/DC step setting register This register is used to set the boost step, etc., of the DC/DC converter. Table 4-16. DC/DC Step Setting Register (R25) - Bit Name Bit 0: VCD2 VCD2 = 0: VDC2 = VDC x 2 VCD2 = 1: VDC2 = VDC x 3 Bit 1: VMS Selects the boost mode for VDC2. VMS = 0: Single boosting mode VMS = 1: Dual boosting mode Bit 2: VRSEL0 Bit 3: VRSEL1 Bit 4: VRSEL2 Selects the VR regulator's output voltage. 4.2.17 DC/DC oscillation setting register This register is used to set the boost frequency, etc., of the DC/DC converter. Table 4-17. DC/DC oscillation setting register (R26) - Bit Name Bit 0: FS0 Bit 1: FS1 selected. Preliminary Product Information S16269EJ2V0PM 33 PD161831 4.2.18 Regulator output setting register This register is used to switch the regulator ON/OFF, set the output voltage, etc. Table 4-18. Regulator Output Setting Register (R27) - Bit Name Bit 0: RGON Controls VS regulator ON/OFF. RGON = 0: VS regulator OFF RGON = 1: VS regulator ON Bit 1: VSEL0 Bit 2: VSEL1 Bit 3: VSEL2 Selects the VS regulator output voltage. 34 Preliminary Product Information S16269EJ2V0PM PD161831 4.2.19 Power supply function LPM setting register This register is used to set the power supply function low-power mode, etc. Table 4-19. Power Supply Function LPM Setting Register (R28) - Bit Name Bit 0: LPM LPM = 0: Normal mode LPM = 1: Low power mode Bit 1: LFS0 Bit 2: LFS1 Selects the VDC2 boost frequency when the power supply function lowpower mode is selected. Preliminary Product Information S16269EJ2V0PM 35 PD161831 4.2.20 DC/DC startup setting register This register is used to set the DC/DC startup time, startup mode, etc. Table 4-20. DC/DC startup Setting Register (R33) - Bit Name Bit 0: PUPT0 Bit 1: PUPT1 Bit 2: DUPF0 Bit 3: DUPF1 For the startup time, refer to table 4-21. Sets the DC/DC operating frequency at DC/DC startup. This bit is effective only when bit 5 (PONM) = 0 and bit 4 (PON) = 1 are set. Table 4-21. DC/DC Rising Time Selection - PONM 1 1 1 1 0 0 PON X X X X 1 0 PUPT0 0 1 0 1 X X PUPT1 0 0 1 1 X X VDC2ON 16/fOSC 16/fOSC 16/fOSC 16/fOSC External input RGONR 2048/fOSC 256/fOSC 512/fOSC 1024/fOSC External input VS1/2ON 1.5 x 2048/fOSC 1.5x 256/fOSC 1.5 x 512/fOSC 1.5 x 1024/fOSC External input VD2ON 2.5 x 2048/fOSC 2.5x 256/fOSC 2.5 x 512/fOSC 2.5 x 1024/fOSC External input Remark Use internal sequence Use internal sequence Use internal sequence Use internal sequence Use external sequence Normal mode Remark X: 0 or 1 4.2.21 Driver output related control signal registers (R36 to R47) These registers set the start timing and the end timing of the active period of the RSW_O, GSW_O, BSW_O, EXT1_O to EXT3_O signals, with the clock obtained by dividing a 1-line horizontal period by 4 as the reference (reference clock of 60 clocks in the case of 1 line consisting of 240 pixels of data). The effective bits of these registers are bit 0 to bit 5, respectively. (Values up to 01H to 3BH can be set.) 36 Preliminary Product Information S16269EJ2V0PM PD161831 4.2.22 EXT1 to EXT3 function setting register EXT1_O outputs each line signal at the timing set with R42 and R43, but for EXTR2_O and EXT3_O, the output cycle can be selected depending on the positive polarity and negative polarity of the common. Table 4-22 shows the concrete details. Moreover, the RSW_O, BSW_O, GSW_O inverted signals can be selected for EXT1_O to EXT3_O. Table 4-22. EXT1 to EXT3 Function Setting Register (R48) - Bit Name Bit 0 Sets the EXT2_O output during line inversion. Bit 0 = 0: Outputs every line Bit 0 = 1: Outputs only line when common is positive. Bit 1 Sets the EXT2_O output during frame inversion. Bit 1 = 0: Outputs every line Bit 1 = 1: Outputs only the first display line for frames when the common is positive. Bit 2 Sets the EXT3_O output during line inversion. Bit 2 = 0: Output every line Bit 2 = 1: Output only lines when the common is negative. Bit 3 Sets the EXT3_O output during frame inversion. Bit 3 = 0: Output every line Bit 3 = 1: Outputs only the first display line for frames when the common is negative. Bit 4 to bit 6 Bit 7 Use prohibited Selects the mode for outputting the RSW_O, GSW_O, and BSW_O inverted signals from EXT1_O to EXT3_O. Bit 7 = 0: Executes the operation set to bit 0 to bit 3. Bit 7 = 1: Outputs the RSW_O, GSW_O, and BSW_O inverted signals from EXT1_O to EXT3_O. EXT1_O = /RSW_O, EXT2_O = /GSW_O, EXT3_O = /BSW_O Mode 4.2.23 GOE1 signal setting registers (R49, R50) These registers set the start timing (R49) and the end timing (R50) of the active period of the GOE1_O signal, with the clock obtained by dividing the 1-line horizontal period by 4 as the reference (reference clock of 60 clocks in the case of 1 line consisting of 240 pixels of data). 4.2.24 Dummy line setting register (R51) This register is used to set whether to perform dummy output to the first line of a frame. In the case of a dummy line, the data input in the immediately preceding line is output. Refer to figure 4-11 and figure 4-12. Table 4-23. Dummy Line Setting Register (R51) - Bit 0 0 1 Mode Dummy line No dummy line Preliminary Product Information S16269EJ2V0PM 37 PD161831 Figure 4-11. Vertical Period GSTB (Top: No dummy line, bottom: Dummy line) - PD161831 display timing chart HSYNC VSYNC GCLK_O GSTB_O GSTB output GOE1_O RSW_O GSW_O BSW_O COMC Valid data input start line 2) dummy line HSYNC VSYNC GCLK_O GSTB_O GSTB output GOE1_O RSW_O GSW_O BSW_O COMC Valid data input start line 38 Preliminary Product Information S16269EJ2V0PM PD161831 Figure 4-12. Vertical Period GSTB (Top: No dummy line, bottom: Dummy line) - PD161831 display timing chart HSYNC VSYNC GCLK_O GSTB_O GSTB output GOE1_O RSW_O GSW_O BSW_O COMC Valid data input start line 2) dummy line HSYNC VSYNC GCLK_O GSTB_O GSTB output GOE1_O RSW_O GSW_O BSW_O COMC Valid data input start line Preliminary Product Information S16269EJ2V0PM 39 PD161831 5. TIMING GENERATOR NON-USE FUNCTION Operation using an external signal without using the on-chip timing generator function is possible by setting the TCON pin (TCON = H). When the timing generator non-use function is selected, data input is performed using the following pins. The concrete timing chart is shown on the following. * DCK: Dot clock * D00 to D05, D10 to D15, D20 to D25: Data bus * STHR, STHL: Data input start pulse * STB: Data latch input * AP: Amplifier drive period control * POL: Polarity inversion signal However, the serial interface can be used, and the common and power supply settings performed with the serial interface. Moreover, when the timing generator non-use function is selected, instead of generating signals through the on-chip timing generator for GCLK_O, GSTB_O, GOE1_O, GOE2_O, RSW_O, GSW_O, BSW_O, and EXT1_O to EXT3_O signals, the signals input from the GCLK_I, GSTB_I, GOE1_I, GOE2_I, RSW_I, GSW_I, BSW_I, and EXT1_I to EXT3_I are output via a level shifter. The signals input to RSW_I, GSW_I, and BSW_I are also used as the amplifier output timing. The level shifter circuit block is divided into the gate control signal side and the driver output related signal side, and it is possible to individually select the negative voltage side voltage level individually from VSS2 and VSS3 at the gate control signal side and the driver output-related signal side. (Refer to 4.2.12 Common amplitude voltage adjustment D/A converter register.) 40 Preliminary Product Information S16269EJ2V0PM Figure 5-1. Data Input Timing Chart When Timing Generator Non-Use Function is Selected (R6, Bit 2 = H) - - - PWCLK CLK PWCLK(L) 1 2 PWCLK(H) 3 240 241 90% tr tf 10% tSPL tSETUP2 tHOLD2 STHR (1st Dr.) (Unless otherwise specified, VIH = 0.7 VDD1, VIL = 0.3 VDD1) tSETUP1 D00 to D05 D10 to D15 D20 to D25 STHL (1st Dr.) INVALID tHOLD1 Last Data INVALID tPLH1 tPHL1 Preliminary Product Information S16269EJ2V0PM tLDT tSETUP4 tHOLD4 PWSTB tSTB-STH tCLK-STB STB POL tPOL-RSW RSW_0 GSW_0 BSW_0 VOUT Hi-Z Hi-Z Hi-Z Hi-Z PD161831 41 PD161831 6. INTERFACE 6.1 RGB Interface The RGB interface has the following two modes: - HSYNC, VSYNC mode Each mode is explained below. 6.1.1 HSYNC, VSYNC mode This mode is used to input display data from the DCK, HSYNC, VSYNC, D05 to D00, D15 to D10, and D25 to D20 pins. In this mode, the value set to the R3 register is valid as the number of valid data in the horizontal period. Figure 6-1 shows the timing chart. Input at least 1 dot clock for the front porch period. Figure 6-1. Timing Chart in HSYNC, VSYNC Mode (When CKS = L, HSEG = L, VSES = L) - VSYNC 1 line period tVBNote HSYNC D05 to D00 D15 to D10 D25 to D20 D05 to D00 D15 to D10 D25 to D20 Invalid 1st line Last line Invalid Invalid 1st pixel 2nd pixel Last pixel Invalid HSYNC 1 pixel period tHBNote DCK D05 to D00 D15 to D10 D25 to D20 Invalid 1st pixel Last pixel Invalid Note tVB = vertical back porch period tHB = horizontal back porch period 42 Preliminary Product Information S16269EJ2V0PM PD161831 6.2 Serial Interface The PD161831 uses an 8-bit serial interface to set registers related to the horizontal period and vertical period from the MCU, and control the timing of outputting strobe signals to the gate driver. In addition, the back panel LCD controller driver can also be controlled. 6.2.1 Serial interface between MCU and PD161831 The serial interface between MCU and PD161831 can acknowledge serial data input (SI), serial clock input (SCLK), and serial data output (SO) if the chip select signal (LCDCS) is active (LCDS = H). This interface supports SPI, and its relationship with the valid edge of the serial clock and the active level of the serial clock can be set by using the SCLEG0 and SCLEG1 pins. Table 6-1. Relationship between Serial Clock and Data - Pin Name Active Level of Serial Clock SCLEG1 L L H H SCLEG0 L H L H Low level Low level High level High level Rising edge of serial clock Falling edge of serial clock Falling edge of serial clock Rising edge of serial clock Falling edge of serial clock Rising edge of serial clock Rising edge of serial clock Falling edge of serial clock Input Timing of Serial Data Output Timing of Serial Data Figure 6-2 shows the signal chart of the serial interface. Figure 6-2. Serial Interface Signal Chart - LCDCS SCLK (SCLEG1 = L) SCLK (SCLEG1 = H) SO & SI (SCLEG0 = L) SO & SI (SCLEG0 = H) A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Serial interface operation specification register transfer Command & data transfer Remarks 1. "" indicates the timing of reading data. 2. If the chip is not active, the shift register and counter are reset to the default status. 3. When wiring SCL, the influence of terminal reflection and external noise due to the wiring length must be taken into consideration. It is recommended to confirm the operation on the actual system. Preliminary Product Information S16269EJ2V0PM 43 PD161831 Figures 6-3 and 6-4 show the relationship between the read/write operation and the SCLEG0 and SCLEG1 pins setting. A read or write operation is specified by a command. When a read operation is specified by a command (A5 bit = 1), the 8-bit data transferred next is read. Figure 6-4 gives a specific example. Be aware that the SO pin becomes Hi-Z at all times other than when data is output. Figure 6-3. Serial Interface Signal Chart (Write sequence) - LCDCS SCLK SI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Serial interface operation specification transfer - Specification of register - Specification of read or write - Selection of back panel LCD function Command & data transfer - Selection of command register - Transfer of set values of command register LCDCS SCLK SI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Serial interface operation specification transfer - Specification of register - Specification of read or write - Selection of back panel LCD function Command & data transfer - Selection of command register - Transfer of set values of command register LCDCS SCLK SI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Serial interface operation specification transfer - Specification of register - Specification of read or write - Selection of back panel LCD function Command & data transfer - Selection of command register - Transfer of set values of command register LCDCS SCLK SI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Serial interface operation specification transfer - Specification of register - Specification of read or write - Selection of back panel LCD function Command & data transfer - Selection of command register - Transfer of set values of command register 44 Preliminary Product Information S16269EJ2V0PM PD161831 Figure 6-4. Serial Interface Signal Chart (Read Sequence) - LCDCS SCLK SI SO Hi-Z A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z Serial interface operation specification register transfer Command & data transfer Hi-Z is entered at LCDCS or the next SCLK input. LCDCS SCLK SI SO A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z Hi-Z Serial interface operation specification register transfer Command & data transfer LCDCS SCLK SI SO A7 A6 A5 A4 A3 A2 A1 A0 D7 Hi-Z D6 D5 D4 D3 D2 D1 D0 Hi-Z Serial interface operation specification register transfer Command & data transfer Hi-Z is entered at LCDCS or the next SCLK input. LCDCS SCLK SI SO Hi-Z A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z Serial interface operation specification register transfer Command & data transfer Preliminary Product Information S16269EJ2V0PM 45 PD161831 6.2.2 Serial interface between PD161831 and back panel LCD Controller Driver This 8-bit serial interface is used to control the back panel LCD. When a function to transfer data to the back panel LCD is selected by a command (A6 bit = 1), the chip select signals (/CS1 and CS2) for the back panel LCD are asserted. When data is input from the SCLK and SI pins to transfer parameters and data, the polarity of the back panel LCD clock (SCLK_SUB) is the low level (high-level start) and data is output from the back panel serial data output line (SO_SUB) at the falling edge of the clock, regardless of the polarity and edge specification of the clock input to SCLK. Bit A0 of the command can be used to specify the level to be output to the A0 pin. If "command specification" is specified by the A0 bit (A0 bit = 0), the A0 pin outputs a low level when the data of the parameter & data register is transferred. If "parameter setting" is specified by the A0 bit (A0 bit = 1), the A0 pin outputs a high level when the data of the parameter & data register is transferred. This interface can be used even in the standby mode. The transfer operation is illustrated below. Figure 6-5. Serial Interface Signal Chart (Access to Back Panel LCD, SCLEG0 = SCLEG1 = H) - Command & data transfer D6 D5 D4 D3 D2 D1 D0 Serial interface operation specification register transfer Transfer to back panel 46 Preliminary Product Information S16269EJ2V0PM PD161831 This interface is effective in the following cases: - When an access to the back panel LCD controller driver is to be (or must be) made by the serial interface. - If the specifications of the internal serial interface of the MCU in the set differ from the specifications of the back panel LCD controller driver. (Even if the serial interface of the MCU does not start when the serial clock is high, output data at the falling edge of the clock, and input data at the rising edge of the clock (frequently used specifications), the serial interface of the PD161831 supports SPI and any input). An example where the back panel serial interface is necessary is given below. Figure 6-6. Example Where Back Panel Serial Interface Is Necessary - PD161831 /CS1, CS2 SO_SUB SCLK Back panel LCD /CS SI SCLK Serial interface This cannot be connected if specifications of serial interface differ. /CS SO SCLK MCU Preliminary Product Information S16269EJ2V0PM 47 PD161831 7. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The PD161831 includes a resistor for normally-black support. The relationship between the input data and the output voltage is shown in figure 7-2. Any 3 major points V1-V3 from the LCD panel -characteristics curve can be used as the external power supplies. The relation V0-V4 external power supplies and correction resistance is shown in table 7-1, figure 7-1. Table 7-1. Relationship between External Power Supplies and Correct Voltage and Resistance - Pin Name V0 V1 V2 V3 V4 Voltage (V) VS 0.7 x VS 0.5 x VS 0.3 x VS 0 Resistance () T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. Figure 7-1. Relationship between External Power Supplies and Correction Resistance - VS VS (V) T.B.D. 0.7 x VS T.B.D. 0.5 x VS T.B.D. 0.3 x VS T.B.D. 0 (V) VSS External power supply pins V0-V4 can be customized at any place of the correction voltage. The string resistance between VSS-VS that generates the correction voltage is divided by 250, from which the desired voltage can be selected and the correction voltage can be customized. In addition, positive or negative polarity can also be selected for each correction voltage. 48 Preliminary Product Information S16269EJ2V0PM PD161831 Table 7-2. Relationship between Input Data and Output Voltage Value - T.B.D. Preliminary Product Information S16269EJ2V0PM 49 PD161831 Figure 7-2. Relationship between Positive/Negative Polarity and Data Output - T.B.D. 50 Preliminary Product Information S16269EJ2V0PM PD161831 8. CONNECTION OF CORRECTION RESISTOR TO POWER SUPPLY AND GND PINS Connection of the correction resistors of the PD161831, correction resistor power supplies (V0-V4) is shown below. Depending on the setting of the GAM pin, the maximum and minimum potential of the correction resistors can be changed between VS-VSS and V0-V4. Figure 8-1. GAM Pin Function - VS SW1 V0 GAM -selection SW Positive Negative polarity polarity GAM = L SW1 SW2 V1 V2 GAM = H V3 SW1 SW2 V4 SW2 GAM VSS Preliminary Product Information S16269EJ2V0PM 51 PD161831 9. -CORRECTION POWER SUPPLY CONNECTION EXAMPLE The PD161831 enables customization of the -correction power supply on both the positive and negative polarity sides (For details, refer to 7. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE). Consequently, a -correction power supply does not have to be input externally when a single source-driver chip is being used in the panel. Figure 9-1. -Correction Power-Supply Connection Example - Single chip V0 V1 V2 V3 V4 PD161831 V0 V1 V2 V3 V4 PD161831 Multiple chip V0 V1 V2 V3 V4 V0 V1 V2 V3 V4 PD161831 PD161831 V0 V1 V2 V3 V4 V0 V1 V2 V3 V4 PD161831 PD161831 52 Preliminary Product Information S16269EJ2V0PM PD161831 10. RESET The PD161831 can be reset by hardware (/RESET pin) or a command (R15 register). A hardware reset resets all the functions, including the registers except serial interface. A command reset initializes only the registers. Be sure to execute a hardware reset and command reset immediately after power application. Each reset is explained below. 10.1 Hardware Reset When a hardware reset is input (/RESET = L), reset is performed for the registers listed in table 4-2 and the on-chip hardware function. (Initialization of the serial interface counter is performed from LCDCS.) Therefore, even when the timing generator non-use mode is selected, be sure to input a hardware reset. While the hardware reset signal is being input (/RESET = L H) and during the period of "VSYNC x 20" after bit 0 of the R24 register has been set to 1 (DCON = 1) after the reset was cleared, all the gate outputs are set to OFF, and the charge on the TFT panel pixels is decreased to 0. Figure 10-1 shows the timing between when the hardware reset signal is input and when display output is produced. Figure 10-1. From Input of Hardware Reset to Display Output - /RESET Command reset GCLK DCON (R24: bit 0) GOE1 A low level is forcibly output for the duration of [VSYNC x 20] after bit 0 of R24 register is set to 1 (DCON = 1) after /RESET is cleared. Set each register while GOE1 = L GOE2 When bit 4 of the R4 register = 0, GOE1 output continues to be low level even after the "VSYNC x 20" period has elapsed after bit 0 of the R24 register is set to 1 (DCON =1). Moreover, if bit 4 of the R4 register is set to "1" before the "VSYNC x 20" period elapses after bit 0 of the R24 register has been set to (DCON = 1), low output is performed from the GOE1 pin until the "VSYNC x 20" time has elapsed. 10.2 Command Reset A command reset (R15 register) only initializes the registers. Preliminary Product Information S16269EJ2V0PM 53 PD161831 11. GOE1 AND GOE2 SIGNALS The output of the GOE1 and GOE2 signals changes according to the setting of the DCON signal and the input of /RESET and standby. -GOE1: After DCON is set to 1 (bit 0 of R24 register is set to 1), the GOE1 signal outputs a low level for a period of "VSYNC x 20", and output of all the gates is switched off. (All gates are off at power application.) -GOE2: In standby mode, when DCON = 0, GOE2 outputs a low level and output of all the gates is switched on. (In standby mode, the charge of the panel is discharged.) Refer to figure 11-1 below for details. Figure 11-1. GOE1 and GOE2 Signal Output - Power supply cut /RESET Standby ON, commands executed Command reset Standby OFF, commands executed DCON (R24: bit 0) GOE1 After bit 0 of R24 register is set to 1 (DCON = 1), a low level is forcibly output for a period of [20 x VSYNC] GOE2 All gates ON All gates OFF All gates ON All gates OFF All gates ON All gates OFF Regarding the GOE1 signal, the above-described function does not work when the timing generator function is not used, and output enable/disable for the GOE1 signal following reset release can be controlled only with the R6 register. 12. POWER SUPPLY ON/OFF SEQUENCE T.B.D. 54 Preliminary Product Information S16269EJ2V0PM PD161831 13. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Logic part supply voltage Driver part supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature VCC VS VI VO TA Tstg Symbol Rating -0.3 to +4.5 -0.3 to +6.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -40 to +85 -55 to +125 Unit V V V V C C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = -40 to +85C, VSS = 0 V) Parameter Logic part supply voltage Driver part supply voltage Booster reference power supply High-level input voltage Low-Level input voltage VCC VS VDC VIH VIL V0-V4 fCLK VCC = 2.5 to 5.5 V VCC = 2.2 to 5.5 V Symbol Condition MIN. 2.2 4.5 2.5 0.7 VCC 0 VSS 5.0 TYP. MAX. 3.6 5.5 3.6 VCC 0.3 VCC VS 20 16 Unit V V V V V V MHz MHz -corrected voltage Clock frequency Preliminary Product Information S16269EJ2V0PM 55 PD161831 5 Electrical Characteristics (TA = -40 to +85C, VCC = 2.2 to 3.6 V, VS = 5.0 V 0.5 V, VSS = 0 V) Parameter Input leak current Input current High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Symbol IIH IIL IIH2 VOH VOL VOH2 VOL2 I IVOH1 IVOL1 Driver output voltage (8-color display mode) Output voltage deviation Output voltage range COMDC output impedance VREF input voltage range VDD1 boost voltage VDC2 boost voltage 1 VDC2 boost voltage 2 VSS2 boost voltage VSS3 boost voltage VDD1 output resistance VDC2 output resistance 1 VDC2 output resistance 2 VSS2 output resistance VSS3 output resistance VS output voltage VR output voltage VS output resistance VR output resistance Logic part static current consumption Logic part dynamic current consumption Driver part static current consumption Driver part dynamic current consumption IDC2 No load, VDC = 2.8 V, VS = 5.0 V No load, VDC = 2.8 V, VS = 5.0 V 8-color mode Note2 Note2 Condition MIN. -1.0 TYP. MAX. 1.0 Unit A A A V V V V Except TESTIN1, TESTIN2 TESTIN1, TESTIN2 Except COMC, IOH = -0.1 mA Except COMC, IOL = +0.1 mA COMC, IOH = -1.0 mA COMC, IOL =+1.0 mA V0 = 5.0 V, V4 = 0 V (GAM = L) VS = 5.0 V, VOUT = VX - 1.0 V Input data: 1FH VS = 5.0 V, VOUT = VX + 1.0 V Input data: 20H VS = 5.0 V, IO = -100 A VS = 5.0 V, IO = +100 A Note1 Note1 1.5 VCC - 0.5 5.0 0.5 T.B.D. T.B.D. 115 230 T.B.D. T.B.D. T.B.D. T.B.D. 10 20 VS - 0.05 T.B.D. 1.7 VS 1.9 VDC 2.8 VDC -1.0 VS -3.0 VS 1.5 50 100 1 1.5 4.5 4.5 3.0 100 200 2 3.0 5.0 5.0 30 T.B.D. 2.0 VS 2.0 VDC 3.0 VDC -0.8 VS -2.7 VS 5.0 200 400 3 5.0 5.5 5.5 60 T.B.D. 10 0.6 T.B.D. 2.6 1.3 0.9 T.B.D. T.B.D. T.B.D. VSS+ 0.05 T.B.D. 460 T.B.D. -correction power-supply static current consumption Driver output current (Amp. drive) A mA mA V V mV V V V V V V V k k k V V VOH3 VOL3 VO VO RCOMDC VREFIN VDD1 VDC2 VDC2 VSS2 VSS3 RVDD1 RVDC21 RVDC22 RVSS2 RVSS3 VS VR RVS RVR ICC1 ICC2 IDC1 RGB data: 00H to 3FH IO = -40 A IDD1 = +300 A VDC2 = L (x2 boost), IDC = +1.0 mA VDC2 = L (x3 boost), IDC = +1.0 mA ISS2 = -300 A ISS3 = -300 A IDD1 = +300 A VDC2 = L (x2 boost), IDC = +1.0 mA VDC2 = L (x3 boost), IDC = +1.0 mA ISS2 = -300 A ISS3 = -300 A No load No load VDC2 = 6.0 V, IS = +1.0 mA, VS = 5.0 V VDC2 = 6.0 V, IR = +1.0 mA, VS = 5.0 V No load, standby mode No load Note2 A mA No load, VDC = 2.8 V, standby mode A mA mA , Notes 1. VX refers to the output voltage of analog output pins S1 to S240. VOUT refers to the voltage applied to analog output pins S1 to S240. 2. fCLK = 15 MHz, STB cycle = 52 s, AP pulse width (each multiplexer switch amplifier driving time) = 10 s, BA = L (low power mode) 56 Preliminary Product Information S16269EJ2V0PM PD161831 Switching Characteristics (TA = -40 to +85C, VCC = 2.2 to 3.6 V, VS = 5.0 V 0.5 V, VSS = 0 V) Parameter Start pulse delay time Driver output delay time (High power mode, with load) Driver output delay time (Low power mode, with load) High capacitance DC/DC oscillation frequency DCCLK input frequency Symbol tPLH1 tPLH2H tPHL2H tPLH2L tPHL2L CI1 CI2 fDCDC fDCCLK CL = 15 pF CL = 30 pF, APVOUT -100 mV, or VOUT+100 mV CL = 30 pF, APVOUT -100 mV, or VOUT+100 mV V0-V4, TA = 25C Except for V0-V4,TA = 25C FS0 = FS1 = H 10 5 10 15 15 Condition MIN. TYP. MAX. 30 12 12 15 15 15 15 20 50 Unit ns s s s s pF pF kHz kHz Preliminary Product Information S16269EJ2V0PM 57 PD161831 RGB interface (1/2) VSYNC 1 line period tVBNote HSYNC D05 to D00 D15 to D10 D25 to D20 D05 to D00 D15 to D10 D25 to D20 Invalid 1st line Last line Invalid Invalid 1st pixel 2nd pixel Last pixel Invalid HSYNC 1 pixel period tHBNote DCK D05 to D00 D15 to D10 D25 to D20 Invalid 1st pixel Last pixel Invalid Note tVB = vertical back porch period tHB = horizontal back porch period 58 Preliminary Product Information S16269EJ2V0PM PD161831 RGB interface (2/2) tV tVP VSYNC tVB tVF Display period tVD tH tHP (HSYNC) tHB tHF Display period tHD tC tCH PCLK 0.5 VCC tDS Data (R0 to R4) (G0 to G4) 0.5 VCC (B0 to B4) tCH Invalid 0 175 Invalid Preliminary Product Information S16269EJ2V0PM 59 PD161831 TA = -40 to +85C, VCC = 2.2 to 3.6 V, VS = 5.0 V 0.5 V, VSS = 0 V Name Clock Frequency Duty Rise/Fall Horizontal signal Cycle Display period Front porch Pulse width Back porch VCC 2.5 V VCC 2.2 V Symbol 1/tC 1/tC tCH/tC tCRF tH tHD tHF tHP tHB 1.0 2.0 2.0 4.0 10.0 T.B.D. T.B.D. - T.B.D. Front porch Pulse width Back porch tVF + tVP + tVB VSYNC setup time VSYNC hold time Data Clock - data timing Data - clock timing tVSS tVSH tDH tDS tVF tVP tVB 1.0 1.0 1.0 4.0 T.B.D. T.B.D. T.B.D. T.B.D. MIN. T.B.D. T.B.D. T.B.D. - - - TYP. 5.0 5.0 0.5 - 50.51 252 240 3.0 5.0 4.0 T.B.D. T.B.D. - - 16.67 330 2.0 5.0 3.0 10.0 - - - - - - - T.B.D. T.B.D. - - - T.B.D. - - - - - - - - MAX. 10.0 8.0 0.6 T.B.D. - - Unit MHz MHz - ns Remark 200 ns (TYP.) 200 ns (TYP.) - - 19.8 kHz (TYP.) - - - - - - - - 60.0 Hz (TYP.) - - - - - - - - s CLK CLK CLK CLK CLK CLK CLK ns ns ms H H H H H ns ns ns ns tHP + tHB (Quarter data function not used) tHP + tHB (Quarter data function used) HSYNC setup time HSYNC hold time Vertical signal Cycle tHSS tHSH tV 60 Preliminary Product Information S16269EJ2V0PM PD161831 Serial Interface * Serial interface between MCU and PD161831 (when SCLEG0 = SCLEG1 = H) tCSS tCSH LCDCS tSCYC tSLW SCLK tf tSDS tr tSHW tSDH SI tSDD SO TA = -40 to +85C, VCC = 2.2 to 3.6 V, VS = 5.0 V 0.5 V, VSS = 0 V Parameter Serial clock cycle SCLK_SUB high-level pulse width SCLK_SUB low-level pulse width Data setup time Data hold time CS - SCL time SCLK SO output delay time Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH tSDD Condition MIN. 150 60 60 60 60 90 90 T.B.D. TYP. Note MAX. Unit ns ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC. Preliminary Product Information S16269EJ2V0PM 61 PD161831 * Serial interface between PD161831 and back panel tCSS2 tCSH2 GCS, /CS1 CS2 tSCYC2 tSLW2 SCLK_SUB tf tSDD2 tr tSHW2 SO_SUB TA = -40 to +85C, VCC = 2.2 to 3.6 V, VS = 5.0 V 0.5 V, VSS = 0 V Parameter Serial clock cycle SCLK_SUB high-level pulse width SCLK_SUB low-level pulse width CS - SCLK_SUB time SCLK_SUB SO_SUB output delay time Symbol tSCYC2 tSHW2 tSLW2 tCSS2 tCSH2 tSDD2 Condition MIN. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. TYP. Note MAX. Unit ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC. 62 Preliminary Product Information S16269EJ2V0PM PD161831 Timing Requirements When not Using Timing Generator T.B.D. Timing Requirements (TA = -40 to +85C, VCC = 2.2 to 3.6 V, VSS = 0 V, tr = tf = 10 ns) Parameter Clock pulse width Clock pulse high time Clock pulse low time Data setup time Data hold time Start pulse setup time Start pulse hold time Start pulse low time Last data timing CLK - STB time STB pulse width Start pulse rising time STB setup time STB hold time POL - RSW_O time AP pulse width (High power mode) AP pulse width (Low power mode) Symbol PWCLK PWCLK(H) PWCLK(L) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSPL tLDT tCLK-STB PWSTB tSTB-STH tSETUP4 tHOLD4 tPOL-RSW PWAPH PWAPL STB cycle = 40 s, CL = 30 pF STB STH CLK STB Condition MIN. 100 30 30 20 20 20 20 3 2 20 40 3 20 20 T.B.D. T.B.D. T.B.D. TYP. MAX. Unit ns ns ns ns ns ns ns CLK CLK ns ns CLK ns ns ns s s Preliminary Product Information S16269EJ2V0PM 63 PD161831 [MEMO] 64 Preliminary Product Information S16269EJ2V0PM PD161831 [MEMO] Preliminary Product Information S16269EJ2V0PM 65 PD161831 [MEMO] 66 Preliminary Product Information S16269EJ2V0PM PD161831 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Product Information S16269EJ2V0PM 67 |
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